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ASAHI KASEI
[AK4357]
AK4357
192kHz 24-Bit 6ch DAC with DSD Input
GENERAL DESCRIPTION The AK4357 is six channels 24bit DAC corresponding to digital audio system. Using AKM's advanced multi bit architecture for its modulator the AK4357 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4357 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4357 accepts 192kHz PCM data and 1-Bit DSD data, ideal for a wide range of applications including DVD-Audio and SACD. FEATURES o Sampling Rate Ranging from 8kHz to 192kHz o 24Bit 8 times Digital Filter with Slow roll-off option o THD+N: -90dB o DR, S/N: 106dB o High Tolerance to Clock Jitter o Low Distortion Differential Output o DSD Data input available o Channel Independent Digital De-emphasis for 32, 44.1 & 48kHz sampling o Zero Detect function o Channel Independent Digital Attenuator with soft-transition (3 Speed mode) o Soft Mute o 3-wire Serial Interface for Volume Control o Master clock: 256fs, 384fs, 512fs or 768fs (PCM Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (PCM Double Speed Mode) 128fs or 192fs (PCM Quad Speed Mode) 512fs or 768fs (DSD Mode) o Power Supply: 4.75 to 5.25V o 48pin LQFP Package
DZF LOUT1+ LOUT1ROUT1+ ROUT1LOUT2+ LOUT2ROUT2+ ROUT2LOUT3+ LOUT3ROUT3+ ROUT3-
SCF SCF
DAC
DATT
Audio I/F
MCLK LRCK BICK SDTI1
DAC
DATT PCM
SDTI2 SDTI3 CSN CCLK CDTI DCLK DSDL1 DSDR1 DSDL2
SCF SCF
DAC
DATT Control Register
DAC
DATT
SCF SCF
DAC DAC
DATT
DATT DSD
AK4357
DSDR2 DSDL3 DSDR3
MS0088-E-02 - 1-
2002/07
ASAHI KASEI
[AK4357]
n Ordering Guide
AK4357VQ AKD4357 -40 +85C 48LQFP Evaluation Board for AK4357
n Pin Layout
ROUT1+ ROUT2+ ROUT3+
LOUT2+
LOUT3+
ROUT1-
ROUT2-
ROUT3-
LOUT2-
LOUT3-
AVSS 38
48
47
46
45
44
43
42
41
40
39
37 36 35 34
AVSS
LOUT1LOUT1+ DZFL1 DAFR1 DZF23 CAD0 CAD1 PDN BICK MCLK DVDD NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Top View
AVSS AVDD VREFH DIF2 DIF1 DIF0 DSDR3 DSDL3 DSDR2 DSDL2 DSDR1 DSDL1
AK4357VQ
33 32 31 30 29 28 27 26 25
SMUTE
CCLK
CDTI
SDTI1
SDTI2
SDTI3
DCLK
CSN
LRCK
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 Pin Name LOUT1LOUT1+ DZFL1 DZFR1 DZF23 CAD0 CAD1 PDN I/O O O O O O I I I Function DAC1 Lch Negative Analog Output Pin DAC1 Lch Positive Analog Output Pin DAC1 Lch Zero Input Detect Pin DAC1 Rch Zero Input Detect Pin DAC2,3 Zero Input Detect Pin Chip Address 0 Pin Chip Address 1 Pin Power-Down Mode Pin When at "L", the AK4357 is in the power-down mode and is held in reset. The AK4357 should always be reset upon power-up. Audio Serial Data Clock Pin Master Clock Input Pin An external TTL clock should be input on this pin.
9 10
BICK MCLK
I I
MS0088-E-02 - 2-
DSDM
DVSS
NC
2002/07
ASAHI KASEI
[AK4357]
Function Digital Power Supply Pin, +4.75 +5.25V NC pin No internal bonding 13 DVSS Digital Ground Pin 14 SDTI1 I DAC1 Audio Serial Data Input Pin 15 SDTI2 I DAC2 Audio Serial Data Input Pin 16 SDTI3 I DAC3 Audio Serial Data Input Pin 17 LRCK I L/R Clock Pin 18 SMUTE I Soft Mute Pin When this pin goes to "H", soft mute cycle is initialized. When returning to "L", the output mute releases. 19 CCLK I Control Data Clock Pin 20 CDTI I Control Data Input Pin 21 CSN I Chip Select Pin 22 DSDM I DSD Mode Enable Pin (Pull-down Pin) "0": PCM mode "1": DSD mode 23 DCLK I DSD Clock Pin 24 NC NC pin No internal bonding 25 DSDL1 I DAC1 DSD Lch Data Input Pin 26 DSDR1 I DAC1 DSD Rch Data Input Pin 27 DSDL2 I DAC2 DSD Lch Data Input Pin 28 DSDR2 I DAC2 DSD Rch Data Input Pin 29 DSDL3 I DAC3 DSD Lch Data Input Pin 30 DSDR3 I DAC3 DSD Rch Data Input Pin 31 DIF0 I Audio Data Interface Format 0 Pin 32 DIF1 I Audio Data Interface Format 1 Pin 33 DIF2 I Audio Data Interface Format 2 Pin 34 VREFH I Positive Voltage Reference Input Pin 35 AVDD Analog Power Supply Pin, +4.75+5.25V 36 AVSS Analog Ground Pin 37 AVSS Analog Ground Pin 38 AVSS Analog Ground Pin 39 ROUT3O DAC3 Rch Negative Analog Output Pin 40 ROUT3+ O DAC3 Rch Positive Analog Output Pin 41 LOUT3O DAC3 Lch Negative Analog Output Pin 42 LOUT3+ O DAC3 Lch Positive Analog Output Pin 43 ROUT2O DAC2 Rch Negative Analog Output Pin 44 ROUT2+ O DAC2 Rch Positive Analog Output Pin 45 LOUT2O DAC2 Lch Negative Analog Output Pin 46 LOUT2+ O DAC2 Lch Positive Analog Output Pin 47 ROUT1O DAC1 Rch Negative Analog Output Pin 48 ROUT1+ O DAC1 Rch Positive Analog Output Pin Note: All input pins except pull-down pin should not be left floating.
No. 11 12
Pin Name DVDD NC
I/O -
MS0088-E-02 - 3-
2002/07
ASAHI KASEI
[AK4357]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog Digital |AVSS-DVSS| (Note 2) Input Current (any pins except for supplies) Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature Note: Symbol A VDD DVDD GND IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 -0.3 -40 -65 max 6.0 6.0 0.3 10 AVDD+0.3 DVDD+0.3 85 150 Units V V V mA V V C C
1. All voltages with respect to ground. 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1) Parameter Power Supplies Analog (Note 3) Digital Voltage Reference Note: Symbol A VDD DVDD VREF min 4.75 4.75 AVDD-0.5 typ 5.0 5.0 max 5.25 5.25 AVDD Units V V V
1. All voltages with respect to ground. 3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0088-E-02 - 4-
2002/07
ASAHI KASEI
[AK4357]
ANALOG CHARACTERISTICS
(Ta=25 C; AVDD, DVDD=5V; VREF=AVDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz 20kHz; R L 4k ; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) THD+N fs=44.1kHz 0dBFS -90 -86 dB BW=20kHz fs=96kHz 0dBFS -88 -84 dB BW=40kHz dB fs=192kHz 0dBFS -86 dB BW=40kHz dB Dynamic Range (-60dBFS with A-weighted) (Note 5) 100 106 dB S/N (A-weighted) (Note 6) 100 106 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy Gain Drift 100 ppm/C 2.35 2.5 2.65 Output Voltage (Note 7) Vpp Load Resistance (Note 8) 4 k Power Supplies Power Supply Current (AVDD+DVDD) Normal Operation (PDN = "H", fs 96kHz) 50 75 mA Normal Operation (PDN = "H", fs=192kHz) 60 85 mA Power-Down Mode (PDN = "L") (Note 9) 10 100 A Note: 4. Measured by Audio Precision System Two. Refer to the evaluation board manual. 5. 100dB at 16bit data. 6. S/N is independent of input bit length. 7. Fu ll scale voltage (0dB). Output voltage scales with the voltage of VREFH pin. AOUT(typ.@0dB)=(AOUT+)-(AOUT-)= 2.5Vpp*VREFH/5.0 8. For AC-load. 8k for DC-load 9. All digital inputs including clock pins (MCLK, BICK and LRCK) are held DVDD or DVSS.
MS0088-E-02 - 5-
2002/07
ASAHI KASEI
[AK4357]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75 5.25V; fs = 44.1kHz; DEM = OFF; SLOW="0"; PCM Mode) Parameter Symbol min typ max Units Digital filter 0.05dB (Note 9) Passband PB 0 20.0 kHz -6.0dB 22.05 kHz Stopband (Note 10) SB 24.1 kHz 0.02 Passband Ripple PR dB Stopband Attenuation SA 54 dB Group Delay (Note 11) GD 19.1 1/fs Digital Filter + SCF 0.2 Frequency Response 20.0kHz Fs=44.1kHz FR dB 0.3 40.0kHz Fs=96kHz FR dB 80.0kHz Fs=192kHz FR +0/ -0.6 dB Notes : 10. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535xfs (@ 0.05dB), SB=0.546xfs. 11. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75~5.25V; fs = 44.1kHz; DEM = OFF; SLOW = "1"; PCM Mode) Parameter Digital Filter Passband Stopband Passband Ripple Stopband Attenuation Group Delay Digital Filter + SCF FR FR FR Note: 12. The passband and stopband frequencies scale with fs. For example, PB = 0.185xfs (@0.04dB), SB = 0.888xfs. 20.0kHz 40.0kHz 80.0kHz Frequency Response fs=44.kHz fs=96kHz fs=192kHz +0/ -5 +0/ -4 +0/ -5 dB dB dB (Note 11) 0.04dB -3.0dB (Note 12) SB PR SA GD 72 19.1 (Note 12) PB 0 39.2 18.2 8.1 0.005 kHz kHz kHz dB dB 1/fs Symbol min Typ max Units
DC CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75 5.25V) Parameter Symbol min High-Level Input Voltage VIH 2.2 Low-Level Input Voltage VIL High-Level Output Voltage (Iout = -80A) VOH DVDD-0.4 Low-Level Output Voltage (Iout = 80A) VOL Input Leakage Current (Note 13) Iin Note: 13. DSDM pin has internal pull-down devices, nominally 100k . Typ max 0.8 0.4 10 Units V V V V A
MS0088-E-02 - 6-
2002/07
ASAHI KASEI
[AK4357]
SWITCHING CHARACTERISTICS
(Ta = 25C; AVDD, DVDD = 4.75 5.25V; CL = 20pF) Parameter Symbol Master Clock Frequency fCLK Duty Cycle dCLK min 2.048 40 Typ 11.2896 max 36.864 60 48 96 192 55 Units MHz % kHz kHz kHz %
LRCK Frequency Normal Speed Mode fsn 8 Double Speed Mode fsd 60 Quad Speed Mode fsq 120 Duty Cycle Duty 45 PCM Audio Interface Timing BICK Period Normal Speed Mode tBCK 1/128fs Double/Quad Speed Mode tBCK 1/64fs BICK Pulse Width Low tBCKL 30 Pulse Width High tBCKH 30 BICK " " to LRCK Edge (Note 13) tBLR 20 LRCK Edge to BICK " " (Note 13) tLRB 20 SDTI Hold Time tSDH 20 SDTI Setup Time tSDS 20 DSD Audio Interface Timing DCLK Period tDCK 1/64fs DCLK Pulse Width Low tDCKL 160 Pulse Width High tDCKH 160 DCLK Edge to DSDL/R (Note 14) tDDD -20 Control Interface Timing CCLK Period tCCK 200 CCLK Pulse Width Low tCCKL 80 Pulse Width High tCCKH 80 CDTI Setup Time tCDS 40 CDTI Hold Time tCDH 40 CSN High Time tCSW 150 CSN " " to CCLK " " tCSS 50 CCLK " " to CSN " " tCSH 50 Reset Timing PDN Pulse Width (Note 15) tPD 150 Notes : 13. BICK rising edge must not occur at the same time as LRCK edge. 14. DSD data transmitting device must meet this time. 15. The AK4357 can be reset by bringing PDN= "L".
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20
MS0088-E-02 - 7-
2002/07
ASAHI KASEI
[AK4357]
n Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
VIH VIL
BICK
VIH VIL tSDS tSDH VIH VIL
SDTI
Audio Serial Interface Timing (PCM Mode)
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR VIH VIL
DCLK
Audio Serial Interface Timing (DSD Normal Mode, DCKB = "0")
MS0088-E-02 - 8-
2002/07
ASAHI KASEI
[AK4357]
tDCK tDCKL tDCKH VIH VIL tDDD DSDL DSDR tDDD VIH VIL
DCLK
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB = "0")
VIH CSN VIL tCSS tCCKL tCCKH VIH VIL tCDS tCDH VIH VIL
CCLK
CDTI
C1
C0
R/W
A4
WRITE Command Input Timing
tCSW VIH CSN VIL tCSH CCLK VIH VIL
CDTI
D3
D2
D1
D0
VIH VIL
WRITE Data Input Timing
tPD
PDN
VIL
Power-down Timing MS0088-E-02 - 92002/07
ASAHI KASEI
[AK4357]
OPERATION OVERVIEW n D/A Conversion Mode
The AK4357 can perform D/A conversion for both PCM data and DSD data. When DSD mode, DSD data can be input from DCLK, DSDL1-3 and DSDR1-3 pins. When PCM mode, PCM data can be input from BICK, SDTI1-3 and LRCK pins. PCM/DSD mode changes by DSDM pin or D/P bit, DSDM pin setting and D/P bit setting are ORed internal. When PCM/DSD mode changes by DSDM pin or D/P bit, the AK4357 should be reset by RSTN bit, PW bit (PW1=PW2=PD3="0") or PDN pin. It takes about 2/fs to 3/fs to change the mode. DSDM pin L H D/P bit 0 1 0 1 DAC Output PCM DSD DSD DSD
Table 1. DSD/PCM Mode Control
n System Clock
1) PCM Mode The external clocks, which are required to operate the AK4357, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS = "0": Register 00H), the sampling speed is set by DFS0/1(Table 2). The frequency of MCLK at each sampling speed is set automatically. (Table 3~5). In Auto Setting Mode (ACKS = "1": Default), as MCLK frequency is detected automatically (Table 6), and the internal master clock becomes the appropriate frequency (Table 7), it is not necessary to set DFS0/1. All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4357 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4357 may draw excess current and may fall into unpredictable operation. This is because the dev ice utilizes dynamic refreshed logic internally. The AK4357 should be reset by PDN= "L" after threse clocks are provided. If the external clocks are not present, the AK4357 should be in the power-down mode (PDN= "L"). After exiting reset(PDN = " ") at power-up etc., the AK4357 is in the power-down mode until MCLK is input. DSD interface signals (DCLK, DSDL1-3, DSDR1-3) are fixed to "H" or "L". DFS1 0 0 1 DFS0 0 1 0 Sampling Rate (fs) Normal Speed Mode Double Speed Mode Quad Speed Mode 8kHz~48kHz 60kHz~96kHz 120kHz~192kHz Default
Table 2. Sampling Speed (Manual Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz
256fs 8.1920MHz 11.2896MHz 12.2880MHz
MCLK 384fs 512fs 12.2880MHz 16.3840MHz 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
768fs 24.5760MHz 33.8688MHz 36.8640MHz
BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Table 3. System Clock Example (Normal Speed Mode @Manual Setting Mode)
MS0088-E-02 - 10 -
2002/07
ASAHI KASEI
[AK4357]
LRCK fs 88.2kHz 96.0kHz
128fs 11.2896MHz 12.2880MHz
MCLK 192fs 256fs 16.9344MHz 22.5792MHz 18.4320MHz 24.5760MHz
384fs 33.8688MHz 36.8640MHz
BICK 64fs 5.6448MHz 6.1440MHz
Table 4. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK fs 176.4kHz 192.0kHz
MCLK 128fs 22.5792MHz 24.5760MHz 192fs 33.8688MHz 36.8640MHz
BICK 64fs 11.2896MHz 12.2880MHz
Table 5. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK 512fs 256fs 128fs 768fs 384fs 192fs
Sampling Speed Normal Double Quad
Table 6. Sampling Speed (Auto Setting Mode)
LRCK fs 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
128fs 22.5792 24.5760
192fs 33.8688 36.8640
MCLK (MHz) 256fs 384fs 22.5792 33.8688 24.5760 36.8640 -
512fs 16.3840 22.5792 24.5760 -
768fs 24.5760 33.8688 36.8640 -
Sampling Speed
Normal
Double Quad
Table 7. System Clock Example (Auto Setting Mode)
2) DSD Mode The external clocks, which are required to operate the AK4357, are MCLK and DCLK. The master clock (MCLK) should be synchronized with DSD clock (DCLK) but the phase is not critic al. The frequency of MCLK is set by DCKS bit. All external clocks (MCLK, DCLK) should always be present whenever the AK4357 is in the normal operation mode (PDN= "H"). If these clocks are not provided, the AK4357 may draw excess current because the device utilizes dynamic refreshed logic internally. The AK4357 should be reset by PDN= "L" after threse clocks are provided. If the external clocks are not present, the AK4357 should be in the power-down mode (PDN= "L"). After exiting reset(PDN = " ") at power-up etc., the AK4357 is in the power-down mode until MCLK is input. PCM interface signals (BICK, LRCK, SDTI1-3) are fixed to "H" or "L". DCKS MCLK DCLK 0 512fs 64fs 1 768fs 64fs
Table 8. System Clock (fs=44.1kHz) MS0088-E-02 - 11 2002/07
ASAHI KASEI
[AK4357]
n Audio Serial Interface Format
1) PCM Mode When PCM mode, data is shifted in via the SDTI1-3 pins using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial data modes . Initial value of DIF0-2 bits is"000", each DIF0-2 bits is ORed with DIF0-2 pins. In all modes the serial data is MSB-first, 2 's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. Mode 0 1 2 3 4 DIF2 0 0 0 0 1 DIF1 0 0 1 1 0 DIF0 0 1 0 1 SDTI Format 16bit LSB Justified 20bit LSB Justified 24bit MSB Justified 24bit I2S Compatible BICK 32fs 40fs 48fs 48fs 48fs Figure Figure 1 Figure 2 Figure 3 Figure 4 Figure 2
0 24bit LSB Justified Table 9. Audio Data Formats
LRCK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
BICK (32fs) SDTI Mode 0
0
15 14
1
6
14
5
15
4
16
3
17
2
1
31
0
0
15 14
1
6
14
5
15
4
16
3
17
2
1
31
0
15 14
0 1
BICK (64fs) SDTI Mode 0
Don't care 15:MSB, 0:LSB 15 14 0 Don't care 15 14 0
Lch Data
Figure 1. Mode 0 Timing
Rch Data
LRCK
0 1 8 9 10 11 12 31 0 1 8 9 10 11 12 31 0 1
BICK (64fs) SDTI Mode 1 SDTI Mode 4
Don't care 19:MSB, 0:LSB Don't care 23 22 21 20 19 0 Don't care 23 22 21 20 19 0 19 0 Don't care 19 0
23:MSB, 0:LSB
Lch Data
Figure 2. Mode 1,4 Timing
Rch Data
MS0088-E-02 - 12 -
2002/07
ASAHI KASEI
[AK4357]
LRCK
0 1 2 22 23 24 30 31 0 1 2 22 23 24 30 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23 22
Lch Data
Figure 3. Mode 2 Timing
Rch Data
LRCK
0 1 2 3 23 24 25 31 0 1 2 3 23 24 25 31 0 1
BICK (64fs) SDTI
23 22 23:MSB, 0:LSB 1 0 Don't care 23 22 1 0 Don't care 23
Lch Data
Figure 4. Mode 3 Timing
Rch Data
2) DSD Mode In case of DSD mode, DIF0-2 are ignored. The frequency of DCLK is fixed to 64fs. DCKB bit can invert the polarity of DCLK.
DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal DSDL,DSDR
Phase Modulation
D0 D0 D1 D2 D3
D1
D1
D2
D2
D3
Figure 5. DSD Mode Timing
MS0088-E-02 - 13 -
2002/07
ASAHI KASEI
[AK4357]
n De -emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15s) and is enabled or disabled with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off. When DSD mode, DEM0-1 is invalid. DEM1 0 0 1 1 DEM0 0 1 0 1 Mode 44.1kHz OFF 48kHz 32kHz Default
Table 8. De-emphasis Filter Control (Normal Speed Mode)
n Output Volume
The AK4357 includes channel independent digital output volumes (ATT) with 128 levels at 0.5dB steps including MUTE. These volumes are in front of the DAC and can attenuate the input data from 0dB to -63dB and mute. Transition time is set by AST1-0 bits(Table12) When changing levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. ATT7-0 FFH FEH FDH : 82H 81H 80H : 02H 01H 00H Attenuation Level 0dB -0.5dB -1.0dB : -62.5dB -63.0dB MUTE (-) : MUTE (- ) MUTE (- ) MUTE (- )
Default
Table 11. Attenuation Level of Output Volume Mode 0 1 2 3 ATS1 0 0 1 1 ATS0 0 1 0 1 ATT speed 1792/fs 896/fs 256/fs 256/fs
Default
Table 12. Transition time of output volume In case Mode0, it takes 1792/ fs to transit from FFH(0dB) to 80H(MUTE). In case Mode1, it takes 896/fs to transit from FFH(0dB) to 80H(MUTE). In case Mode2 and 3,it takes 256/fs to transit from FFH(0dB) to 80H (MUTE). If PDN pin goes to "L", ATT7-0 registers are initialized to FFH.ATTN7-0 registers go to FFH when RSTN bit is set to "0". When RSTN bit returns to "1", ATT7-0 registers go to the set value. Digital output volume function is independent of soft mute function. The setting value of the register is held when switching between PCM mode and DSD mode.
MS0088-E-02 - 14 -
2002/07
ASAHI KASEI
[AK4357]
n Zero Detection
When the input data atall channels are continuously zero s for 8192 LRCK cycles,The AK4357 has Zero Detection like Table 13. DZF pin immediately goes to " L" if input data of each channel is not zero after going DZF " H". If RSTN bit is "0", DZF pin goes to " H". DZF pin goes to " L" at 4~5LRCK if input data of each channel is not zero afterRSTN bit returns to " 1". Zero detect function can be disabled by DZFE bit. In this case, DZF pins of both channels are always " L". DZFB bit can invert the polarity of DZF pin. When one of PW1-3 bit is set to "0", the input data of DAC which the PW bit is set to "0" should be zero in order to enable zero detectionof the other channels . When all PW1-3 bits are set to "0", DZF pin fixes "L". When DZFM bit set to "1", only the input data at all channels are continuously zero s for 8192 LRCK cycles, all DZF pins go to "H". DZF Pin Operations DZFL1 When Lch Data of DAC1 is "0", DZFL1 pin goes "H". DZFR1 When Rch Data of DAC1 is "0", DZFR1 pin goes "H". DZF23 When all Lch and Rch Data of DAC2,3 are "0", DZF23 goes "H". Table 13. DZF pin Operations
n Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to "1", the output signal is attenuated by - during ATT_DATAx ATT transition time (Table 12) from the current ATT level. When the SMUTE bit is returned to"0", the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA x ATT transition time. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission.
SMUTE bit (1) (1) (3)
ATT Level Attenuation
-
GD (2) AOUT GD
DZF pin
(4) 8192/fs
Notes: (1) ATT_DATA x ATT transition time (Table 12). For example, in Normal Speed Mode, this time is 1792LRCK cycles (1792/fs) at ATT_DATA=128. (2) The analog output corresponding to the digital input has a group delay, GD. (3) If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to ATT level by the same cycle. (4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to "H". DZF pin immediately goes to "L" if input data are not zero after going DZF "H". Figure 6. Soft Mute and Zero Detection
MS0088-E-02 - 15 -
2002/07
ASAHI KASEI
[AK4357]
n System Reset
The AK4357 should be reset once by bringing PDN= "L" upon power-up. The analog section exits power-down mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during 4/fs.
n Power-down
The AK4357 is placed in the power-down mode by bringing PDN pin "L" and the anlog outputs are floating (Hi-Z). Figure 6 shows an example of the system timing at the power-down and power-up. Each DAC can be powered down by each power-down bit (PW1-3) "0". In this case, the internal register values are not initialized and the analog output is Hi-Z. Because some click noise occurs, the analog output should be muted externally if the click noise influences system application.
PDN
Internal State D/A In (Digital)
GD
Normal Operation
Power-down
Normal Operation
"0" data
(1)
GD
D/A Out (Analog)
Clock In
MCLK, LRCK, BICK
(3) (4)
(2)
(3)
(1)
Don't care
DZF External MUTE
(6)
(5)
Mute ON
Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs are floating (Hi -Z) at the power-down mode. (3) Click noise occurs at the edge of PDN signal. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = "L"). (5) Please mute the analog output externally if the click noise (3) influence system application. The timing example is shown in this figure. (6) DZF pins are "L" in the power-down mode (PDN = "L"). Figure 7. Power-down/up Sequence Example
MS0088-E-02 - 16 -
2002/07
ASAHI KASEI
[AK4357]
n Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to VCOM voltage and DZFL/DZFR pins go to "H". Figure 8 shows the example of reset by RSTN bit.
RSTN bit
3~4/fs (6) 2~3/fs (6)
Internal RSTN bit Internal State D/A In (Digital) (1) D/A Out (Analog)
Clock In
MCLK,LRCK,BICK
Normal Operation
Digital Block Power-down
Normal Operation
"0" data GD GD
(3)
(2) (4)
Don't care
(3)
(1)
2/fs(5)
DZF Notes: (1) The analog output corresponding to digital input has the group delay (GD). (2) Analog outputs go to VCOM voltage. (3) Click noise occurs at the edges(" ") of the internal timing of RSTN bit. This noise is output even if "0" data is input. (4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = "L"). (5) DZF pins go to "H" when the RSTN bit becomes "0", and go to "L" at 2/fs after RSTN bit becomes "1". (6) There is a delay, 3~4/fs from RSTN bit "0" to the internal RSTN bit "0", and 2~3/fs from RSTN bit "1" to the internal RSTN "1". Figure 8. Reset Sequence Example
MS0088-E-02 - 17 -
2002/07
ASAHI KASEI
[AK4357]
n D/A conversion mode switching timing
RSTN bit
4/fs
D/A Mode
PCM Mode 0
DSD Mode
D/A Data
PCM Data
DSD Data
Figure 9. D/A Mode Switching Timing (PCM to DSD)
RSTN bit
D/A Mode
DSD Mode 4/fs
PCM Mode
D/A Data
DSD Data
PCM Data
Figure 10. D/A Mode Switching Mode Timing (DSD to PCM)
Caution: In DSD mode, the signal level is ranging from 25% to 75%. Peak levels of DSD signal above this duty are not recommended by SACD format book (Scarlet Book).
MS0088-E-02 - 18 -
2002/07
ASAHI KASEI
[AK4357]
n Mode Control Interface
Internal registers may be written by 3-wire P interface pins, CSN, CCLK and CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to "01"), Read/Write (1bit; fixed to "1", Write only), Register Address (M SB first, 5bits) and Control Data (MSB first, 8bits). The AK4357 latches the data on the rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN "". The clock speed of CCLK is 5MHz (max). PDN = "L" resets the registers to their default values. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0: Chip Address (C1=CAD1, C0=CAD0) R/W: READ/WRITE (Fixed to "1", Write only) A4-A0: Register Address D7-D0: Control Data Figure 11. Control I/F Timing *The AK4357 does not support the read command and chip address. *When the AK4357 is in the power down mode (PDN = "L") or the MCLK is not provided, writing into the control register is inhibited.
n Register Map
Addr 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH Register Name Control 1 Control 2
Speed & Power Down Control
De-emphasis Control LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Control 3
D7 ACKS 0 0 0 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 0
D6 SLOW 0 0 0 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 0
D5 DZFM 0 DFS1
0
D4 DZFE 0 DFS0
0
D3 DIF2 0 PW3
0
D2 DIF1 0 PW2
0
D1 DIF0
SMUTE
PW1
DEM1
D0 RSTN RSTN RSTN
DEM0
ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 DCKS
ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 D/P
ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 DCKB
ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 DZFB
ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 ATS1
ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 ATS0
Note: For addresses from 0BH to 1FH, data must not be written. When PDN goes to "L", the registers are initialized to their default values. When RSTN bit goes to "0", the only internal timing is reset, and the registers are not initialized totheir default values. All data can be written to the registers even if PW1-3 or RSTN bit is "0".
MS0088-E-02 - 19 -
2002/07
ASAHI KASEI
[AK4357]
n Register Definitions
Addr Register Name 00H Control 1 Default D7 ACKS 1 D6 SLOW 0 D5 DZFM 0 D4 DZFE 1 D3 DIF2 0 D2 DIF1 0 D1 DIF0 0 D0 RSTN 1
RSTN: In ternal timing reset 0: Reset. All DZF pins go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit. DIF2-0: Audio data interface modes (See Table 9, PCM Only) Initial: "000", Mode 0 Register bits of DIF2-0 are ORed with the DIF2-0 pins. DZFE: Data Zero Detect Enable 0: Disable 1: Enable Zero detect function can be disabled by DZFE bit "0". In this case, the DZF pins are always "L". DZFM: Data Zero Detect Mode 0: Channel Separated Mode (See table 13.) 1: Channel ANDed Mode If the DZFM bit is set to "1", all DZF pins go to "H" only when the input data at all channels are continuously zeros for 8192 LRCK cycles. SLOW: Slow Roll-off Filter Enable (PCM Only) 0: Sharp Roll-off Filter 1: Slow Roll-off Filter ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit "1". In this case, the setting of DFS1-0 are ignored. When this bit is "0", DFS1-0 set the sampling speed mode.
Addr Register Name 01H Control 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1
SMUTE
0
D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All DZF pins of go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit. SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft -muted
MS0088-E-02 - 20 -
2002/07
ASAHI KASEI
[AK4357]
Addr Register Name 02H Speed & Power Down Control Default
D7 0 0
D6 0 0
D5 DFS1 0
D4 DFS0 0
D3 PW3 1
D2 PW2 1
D1 PW1 1
D0 RSTN 1
RSTN: Internal timing reset 0: Reset. All DZF pins go to "H" and any registers are not initialized. 1: Normal operation When MCLK frequency or DFS change s , the AK4357 should be reset by PDN pin or RSTN bit. PW3-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 All sections are powered-down by PW1=PW2=PW3=0. DFS1-0:Sampling speed control (See Table 2, PCM Only) 00: Normal speed 01: Double speed 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. Addr Register Name 03H De-emphasis Control Default D7 0 0 D6 0 0 D5
0
D4
0
D3
0
D2
0
D1
DEM1
D0
DEM0
0
0
0
0
0
1
DEM1-0: De-emphasis response control for DAC1/2/3 data on SDTI1/2/3/ (See Table 10, PCM only) Initial: "01", OFF
MS0088-E-02 - 21 -
2002/07
ASAHI KASEI
[AK4357]
Addr 04H 05H 06H 07H 08H 09H
Register Name LOUT1 ATT Control ROUT1 ATT Control LOUT2 ATT Control ROUT2 ATT Control LOUT3 ATT Control ROUT3 ATT Control Default
D7 ATT7 ATT7 ATT7 ATT7 ATT7 ATT7 1
D6 ATT6 ATT6 ATT6 ATT6 ATT6 ATT6 1
D5 ATT5 ATT5 ATT5 ATT5 ATT5 ATT5 1
D4 ATT4 ATT4 ATT4 ATT4 ATT4 ATT4 1
D3 ATT3 ATT3 ATT3 ATT3 ATT3 ATT3 1
D2 ATT2 ATT2 ATT2 ATT2 ATT2 ATT2 1
D1 ATT1 ATT1 ATT1 ATT1 ATT1 ATT1 1
D0 ATT0 ATT0 ATT0 ATT0 ATT0 ATT0 1
ATT7-0: Attenuation Level 128 levels, 0.5dB step (See Table 11)
Addr Register Name 0AH Control 3 Default
D7 0 0
D6 0 0
D5 DCKS 0
D4 D/P 0
D3 DCKB 0
D2 DZFB 0
D1 ATS1 0
D0 ATS0 0
ATS1-0: DATT Speed Setting (See Table 12) Initial: "00", mode 0 DZFB: Inverting Enable of DZF 0: DZF goes "H" at Zero Detection 1: DZF goes "L" at Zero Detection DCKB: Polarity of DCLK (DSD Only) 0: DSD data is output from DCLK falling edge 1: DSD data is output from DCLK rising edge D/P: DSD/PCM Mode Select 0: PCM Mode. SCLK, SDTI1-3, LRCK 1: DSD Mode. DCLK, DSDL1-3, DSDR1-3 D/P bit is ORed with the DSDM pin.When D/P changes , the AK4357 should be reset by PDN pin, PW bit or RSTN bit. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs 1: 768fs
MS0088-E-02 - 22 -
2002/07
ASAHI KASEI
[AK4357]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. An evaluation board (AKD4357) is available in order to allow an easy study on the layout of a surrounding circuit.
+ 10u
Digital 5V
0.1u
Reset Clock
NC 12 D V D D 11 MCLK 10 BICK 9 CAD1 7 CAD0 6
Gen
8
5
4
3
2
1
DZFR1
DZF23
DZFL1
LOUT1-
LOUT1+
PDN
LPF
ROUT1+
MUTE
L1ch OUT R1ch OUT L2ch OUT R2ch OUT L3ch OUT R3ch OUT
13 DVSS 14 SDTI1
48 LPF
MUTE
ROUT1- 47 LOUT2+ LOUT246 45
DSP
15 SDTI2 16 SDTI3 17 L R C K 18 SMUTE 19 CCLK
LPF
MUTE
AK4357
ROUT2+ 44 ROUT2- 43 LOUT3+ 42 41 LPF LPF
MUTE
MUTE
uP
20 CDTI 21 CSN 22 D S D M 23 DCLK 26 DSDR1 28 DSDR2
Top View
LOUT3-
ROUT3+ 40 ROUT3- 39 AVSS 38 30 DSDR3 34 VREFH 27 DSDL2 29 DSDL3 35 AVDD 36 AVSS AVSS 37 31 DIF0 32 DIF1 33 DIF2 LPF MUTE
DSD Data Controller
25 DSDL1
24 NC
+ 0.1u 10u
Analog 5V
Mode Control
System Ground
Analog Ground
Figure 12. Typical Connection Diagram Notes: - LRCK = fs, BICK = 64fs. - When AOUT drives some capacitive load, some resistor should be added in series between AOUT and capacitive load. - All input pins except pull-down pins should not be left floating.
MS0088-E-02 - 23 -
2002/07
ASAHI KASEI
[AK4357]
Digital Ground
Analog Ground
NC 12 DVDD 1 1 10 9 8 7 6 5 4 3 2 LOUT1+ DZF23 DZFL1 LOUT1BICK CAD1 CAD0 1 ROUT1+ 4 8 ROUT1LOUT2+ LOUT247 46 45 ROUT2+ 4 4 ROUT2LOUT3+ LOUT343 42 41 ROUT3+ 4 0 ROUT3AVSS 3 4 VREFH 2 6 DSDR1 2 8 DSDR2 3 0 DSDR3 2 5 DSDL1 2 7 DSDL2 2 9 DSDL3 AVSS 3 5 AVDD 3 6 AVSS 39 38 37
1 3 DVSS
System Controller
1 4 SDTI1 1 5 SDTI2 1 6 SDTI3 1 7 LRCK 1 8 SMUTE 1 9 CCLK 2 0 CDTI 2 1 CSN 2 2 DSDM 2 3 DCLK 24 NC
AK4357
3 1 DIF0
3 2 DIF1
Figure 13. Ground Layout
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually supplied from analog supply in system and should be separated from system digital supply. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS and DVSS of the AK4357 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitor, especially 0.1F ceramic capacitor for high frequency should be placed as near to AVDD and DVDD as possible.
2. Voltage Reference
VREFH sets the analog output range. VREFH pin is normally connected to AVDD with a 0.1F ceramic capacitor. All signals, especially clocks, should be kept away from the VREFH pin in order to avoid unwanted coupling into the AK4357.
3. Analog Outputs
The analog outputs are full-differential outputs and 0.5 x VREFH Vpp (typ) centered around the internal common voltage (about AVDD/2). The differential outputs are summed externally, VAOUT=(AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output range is 5.0Vpp (typ @VREFH=5V). The bias voltage of the external summing circuit is supplied externally. The input data format is 2's complement. The output voltage(VAOUT) is a positive full scale for 7FFFFF (@24bit) and a negative full scale for 800000H (@24bit). The ideal VAOUT is 0V for 000000H (@24bit). The internal switched-capacitor filter and external low pass filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. DC offset on AOUT+/ - is eliminated without AC coupling since the analog outputs are differential.
MS0088-E-02 - 24 -
3 3 DIF2
DZFR1
MCLK
PDN
2002/07
ASAHI KASEI
[AK4357]
4. External Analog Filter
It is recommended by SACD format book (Scarlet Book) that the filter response at SACD playback is an analog low pass filter with a cut -off frequency of maximum 50kHz and a slop of minimum 30dB/Oct. The AK4357 can achieve this filter response by combination of the internal filter (Table 14) and an external filter (Figure 14). Frequency 20kHz 50kHz 100kHz Gain -0.4dB -2.8dB -15.5dB
Table 14. Internal Filter Response at DSD mode
47u
AOUT2.5Vpp
2.0k
1.8k 1.0k 2200p
4.3k 270p
+Vop
3300p 1.8k 1.0k
47u
2.0k
+
AOUT+
2.5Vpp
4.3k 270p
Analog Out
5.65Vpp
-Vop
Figure 14. External 3rd order LPF Circuit Example Frequency Gain 20kHz -0.05dBr 50kHz -0.51dBr 100kHz -16.8dBr DC gain = 1.07dB Table 15. 3rd order LPF (Figure 14) Response
MS0088-E-02 - 25 -
2002/07
ASAHI KASEI
[AK4357]
PACKAGE
48pin LQFP(Unit:mm)
9.0 0.2 7.0 36 25 24 9.0 0.2
1.70Max 0.13 0.13 1.40 0.05
37
48 1 0.22 0.08 12
13
7.0
0.145 0.05 0.5 0.10 M
0 10
0.10
0.5 0.2
n Package & Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0088-E-02 - 26 -
2002/07
ASAHI KASEI
[AK4357]
MARKING
AKM
AK4357VQ XXXXXXX JAPAN
1
1) Asahi Kasei Logo 2) Marking Code: AK4357VQ 3) Date Code: XXXXXXX(7 digits) 4) Country of Origin 5) Pin #1 indication
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license o r other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one d esigned or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant in jury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing i t, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that pa rty in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0088-E-02 - 27 2002/07

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